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Thread switch through TRAP0 and nested EIINT, FPU context and fault dumps. Signed-off-by: Parthiban Nallathambi <[email protected]>
Startup code, INTC, OSTM and RLIN3 UART drivers and the U2C SoC setup. Signed-off-by: Parthiban Nallathambi <[email protected]>
RH850/U2C8 on the QEMU rh850-u2c machine, msh on RLIN311. Signed-off-by: Parthiban Nallathambi <[email protected]>
Hard and soft float builds and kernel utests with toolchain v1.1.0. Signed-off-by: Parthiban Nallathambi <[email protected]>
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📌 Code Review Assignment🏷️ Tag: bsp_renesasReviewers: @kurisaW Changed Files (Click to expand)
🏷️ Tag: workflowReviewers: @Rbb666 @kurisaW @supperthomas Changed Files (Click to expand)
📊 Current Review Status (Last Updated: 2026-11-07 04:41 CST)
📝 Review Instructions
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为什么提交这份PR (why to submit this PR)
Add support for the Renesas RH850 G4KH core, tested on the QEMU rh850-u2c machine.
你的解决方案是什么 (what is your solution)
Draft: the utest CI needs a ctime.c fix for picolibc first (separate PR).
Tested on QEMU with toolchain v1.1.0 (GCC 14.3, picolibc) and qemu-rh850 v1.0.0: msh boots, kernel_basic 22/22, mem and ipc utests pass, hard and soft float.
请提供验证的bsp和config (provide the config and bsp)
BSP: bsp/renesas/rh850/qemu-rh850-u2c
.config: default. Soft float: RT_USING_FPU=n
action: